1. Field of the Invention
The present invention relates to a technology pertaining to a bit line precharge-type semiconductor read only memory.
2. Description of the Related Art
Conventionally, a bit line precharge-type read only memory has been used in which data are stored according to whether or not there is a transistor connected to a bit line and the stored data are read out by detecting the potential of the bit line that has been precharged. Specifically, this type of read only memory has such a configuration as shown in FIG. 9.
As seen in the figure, precharge transistors Tr810 to Tr8n0, which constitutes a precharge circuit, are so configured as to precharge bit lines B810 to B8n0 under the control of a precharge signal 800.
Word lines W801 to W80m are respectively connected to the gates of N-channel MOS transistors Tr811 to Tr8nm, which constitute columns of transistors. More specifically, for example, the word line W801 is connected to the gates of the N-channel MOS transistors Tr811 to Tr8n1, the word line W802 is connected to the gates of the N-channel MOS transistors Tr812 to Tr8n2, and the word line W80m is connected to the gates of the N-channel MOS transistors Tr81m to Tr8nm.
The sources of the N-channel MOS transistors Tr811, etc. are grounded, whereas the drains are either connected to or cut off from the corresponding bit lines B810 to B8n0 according to the data (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) to be recorded, Specifically, in the example shown in the figure, drains of N-channel MOS transistors Tr811, etc. are connected to the bit lines B110, etc. in the cases where data to be recorded are xe2x80x9c0xe2x80x9d. Accordingly, when these N-channel MOS transistors, Tr811, etc. are tuned ON during read-out, the potentials of the bit lines B810, etc. to which the drains of the N-channel MOS transistors Tr811, etc. are connected are changed to a low level (xe2x80x9cLxe2x80x9d level).
P-channel MOS transistors Tr911 to Tr9n1 constitute pull-up circuits, and the drive capability of each of these P-channel MOS transistors is determined so that when data xe2x80x9c1xe2x80x9d is read out (i.e., when the drains of the N-channel MOS transistors Tr812, etc. that are turned ON are not connected to the bit lines B810, etc.), the potentials of the bit lines B810 to B8n0 are maintained at a high level (xe2x80x9cHxe2x80x9d level), and that the drive capability is less than that of the N-channel MOS transistors Tr811, etc.
The bit lines B810 to B8n0 are respectively connected to inverter circuits Inv811 and Inv812 to Inv8n1 and Inv8n2, which constitute output circuits.
In the read only memory as described above, data are read out according to the following operation.
(1) First, as shown in FIG. 10, the precharge signal 800 is reduced to an xe2x80x9cLxe2x80x9d level, the precharge transistors Tr810, etc. are switched to an ON state, and each of the bit lines B810 are precharged to an xe2x80x9c1xe2x80x9d level.
(2) Thereafter, in response to an input address signal (not shown), one of the word lines W801, etc. is selected and turns to an xe2x80x9cHxe2x80x9d level.
(3) Then, for example, when the word line W802 is selected and turns to an xe2x80x9cHxe2x80x9d level, the N-channel MOS transistors Tr812 to Tr8n2 that are connected to the word line W802 are switched to an ON state.
In this case, the drain of the N-channel MOS transistor Tr812 that is switched to an ON state is not connected to the bit line B810, and therefore, the potential of the bit line B810 is maintained at the xe2x80x9cHxe2x80x9d level by the P-channel MOS transistor Tr911 even after the precharge signal 800 has changed to the xe2x80x9cHxe2x80x9d level. Thus, a data xe2x80x9c1xe2x80x9d is output via the inverter circuits Inv811 and Inv812.
Meanwhile, the drain of the N-channel MOS transistor Tr822 that is also switched to an ON state is connected to the bit line B820 and, in addition, the drive capability of the P-channel MOS transistor Tr921 is made lower than the N-channel MOS transistor Tr822, as mentioned above. Therefore, the bit line B810 is discharged and the potential is reduced to an xe2x80x9cLxe2x80x9d level. Thus, a data xe2x80x9c0xe2x80x9d is output via the inverter Inv821 and Inb822.
In recent years, miniaturization has advanced in the process for CMOS semiconductor integrated circuit, and the power supply voltage has been more and more scaled as the thickness of the gate oxide film reduces. In order to avoid a operating speed reduction caused by the decrease of power supply voltage, there has been a trend toward reduction in threshold voltages of MOS transistors.
When the threshold voltage is reduced, however, the off leakage current of a MOS transistor increases. Consequently, in read only memories in which a number of drain nodes are connected to bit lines, the potentials of the bit lines tend to fluctuate, often causing device malfunctions. For example, in read only memories, the number of N-channel MOS transistors that are connected to bit lines often exceeds 1000, and therefore, even if the leakage current of each transistor is small, the total of the leakage current well exceeds a negligible level and affects circuit operation to cause malfunctions.
More specifically, assuming a case, for example, where there are a large number of the N-channel MOS transistors Tr811, etc. whose drains are connected to the bit line 810 (i.e., a case where many data xe2x80x9c0xe2x80x9ds are written), when the word line W802 turns to an xe2x80x9cHxe2x80x9d level as described above, then the potential of the bit line B810 cannot be maintained at the xe2x80x9cHxe2x80x9d level, as shown by the dashed line in FIG. 10 and results in an output data xe2x80x9c0xe2x80x9d, when the total of the off leakage currents of the N-channel MOS transistors Tr811 to Tr81m (except Tr812) exceeds the current that the pull-up circuit can supply (i.e., exceeds the drive capability), even though the drain of the N-channel MOS transistor Tr812 is not connected to the bit line B810 (i.e., even though a data xe2x80x9c1xe2x80x9d has been written therein). This phenomenon is apt to occur particularly at high temperatures, at which the off leakage current increases.
On the other hand, if the drive capability of the pull-up circuit is increased to prevent such a malfunction as described above, the discharge operation by the N-channel MOS transistor Tr822 is hindered by the pull-up circuit in the bit line B820, which is supposed to output a data xe2x80x9c0,xe2x80x9d and a time lag until the bit line B820 reaches the xe2x80x9cLxe2x80x9d level becomes long as shown by the dash-dot line in FIG. 9. This causes an increase in access time during read-out.
Moreover, as the potential of the bit line B820 is reduced by discharging, the voltage between the source and the drain of the P-channel MOS transistor Tr921 (pull-up circuit) increases, thereby increasing the current supplied to the bit line B820. As a result, the potential of the bit line B820 cannot be reduced below the threshold level of the inverter circuit Inv821, further increasing the possibility of malfunctions.
In view of the foregoing and other problems, it is an object of the present invention to reliably prevent malfunctions of read only memories caused by, for example, off leakage current of transistors without increasing access time.
This and other objects are accomplished, in accordance with a first aspect of the present invention, by providing a read only memory having a plurality of bit lines, a plurality of word lines, and a plurality of switching elements, wherein data corresponding to the presence or absence of switching elements connected to the bit lines are read out by discharging electric charge precharged in the bit lines with the switching elements selected by the word lines, the read only memory comprising: at least one current supplying circuit that supplies current to one of the bit lines when the switching elements are selected by the word lines; wherein the current supplying capability of the current supplying circuit is determined according to the number of the switching elements connected to the one of the bit lines.
With this configuration, the off leakage current of the switching elements that are not selected by the word lines is appropriately compensated sufficiently but not excessively by the current supplying circuit having a current supplying capability according to the number of the switching elements. Specifically, when the number of the switching elements connected to a bit line is large, the current supplying capability of the current supplying circuit that supplies current to the bit line is determined to be large, so that malfunctions caused by a decrease in the potential of the bit line can be prevented, whereas when the number of the switching elements connected to a bit line is small, the current supplying capability is determined to be small, so that malfunctions and operation speed degradations can be prevented that are caused by the obstruction to the discharge operation of the switching elements that are selected by word lines and are switched to an ON state.
In the above-described read only memory, the current supplying circuit may be a constant current circuit.
With this configuration, even if the potential of the bit line is reduced by the discharge of the switching elements that are selected and turned ON by the word lines, the potential of the bit line can be reliably reduced because the supplied current does not fluctuate. Specifically, in the case where a current is supplied to a bit line by a MOS transistor, as the potential of the bit line decreases, the supplied current increases since the voltage between the source and the drain of the MOS transistor increases. Therefore, the potential of the bit line cannot be sufficiently reduced, and the margins for switching levels of the output circuit tend to be small. In view of this, as described above, when a current is supplied to the bit line using a constant current circuit, the supplied current does not increase even if the potential of the bit line decreases. Thus, the potential of the bit line can be quickly and sufficiently reduced and consequently, operation speed is improved while margins of the output circuit are increased.
In the above-described read only memory, the constant current circuit may include a reference current generating circuit for generating a predetermined reference current using the same type of switching element as the switching elements; and a current mirror circuit for mirroring the reference current and supplying electric current to the bit line; wherein the mirror ratio of the current mirror circuit is determined according to the number of the switching elements.
With this configuration, since the current mirror circuit can supply a constant current that is proportional to a reference current, a constant current according to the number of the switching element connected to a bit line can be easily supplied to the bit line by appropriately determining the mirror ratio. In addition, since a current is supplied to the bit line using the current generated by a switching element of the same type as the switching element connected the bit line as a reference current, the off leakage current of the switching elements connected to the bit line can be easily compensated appropriately. Specifically, the use of a current mirror circuit makes it possible to supply a current for compensating an off leakage current, for example, using off transistors having characteristics corresponding to the transistors connected to the bit line (temperature characteristics and power supply voltage characteristics). Therefore, in comparison with conventional cases in which an on current of transistors is supplied, the accuracy of current compensation can be more easily increased without carrying out difficult matching of characteristics. Moreover, the off leakage current can be effectively cancelled against fluctuations in ambient conditions such as power supply voltages and ambient temperatures.
In the above-described read only memory, the current supplying circuit may supply an electric current to the bit line when the potential of the bit line is higher than a predetermined potential whereas the current supplying circuit may cut off electric current to the bit line when the potential of the bit line is lower than the predetermined potential.
With this configuration, the current supply is stopped when the potential of the bit line is reduced to a lower potential than a predetermined potential by the discharge of the switching elements selected by word lines and turned ON, and therefore, the potential of the bit line can be reduced more quickly and reliably thereafter. Consequently, margins in discharge operations can be increased.
In the above-described read only memory, the numbers of the switching elements to be connected to the bit lines may be categorized into a plurality of groups, and the current supplying capability of the current supplying circuit may be determined according to the groups.
With this configuration, the variety of current supplying circuits having differing current capabilities can be reduced, and therefore, simplification of the configurations can be easily achieved.
The above-described read only memory may further have a current adjusting circuit for adjusting the current supplying capability according to the potential of the bit line when all the switching element connected to the bit line are in an OFF state.
In the above-described read only memory, the current adjusting circuit may include a comparator circuit that compares the potential of the bit line with a predetermined reference potential when all the switching elements connected to the bit line are in an OFF state; a holding circuit that holds a comparison result obtained by the comparator circuit; and an adjusted current supplying circuit that supplies a current to the bit line according to the data held in the holding circuit.
With these configurations, even when the off leakage current fluctuates, for example, due to variations of the off leakage characteristics of the switching elements, a current corresponding to the fluctuating off leakage current can be supplied to the bit line by, for example, monitoring the potential of the bit line when the switching elements are in an OFF state. Therefore, a discrepancy between the off leakage current and the supplied current is suppressed and the off leakage current can be compensated more reliably.
In accordance with another aspect of the present invention, a read only memory is provided having a plurality of bit lines, a plurality of word lines, and a plurality of switching elements, wherein data corresponding to the presence or absence of switching elements connected to the bit lines are read out by discharging electric charge precharged in the bit lines with the switching elements selected by the word lines, the read only memory comprising: a plurality of current supplying portions that constitute a current supplying circuit having a predetermined current supplying capability and supplying electric current when the switching elements are selected to the word line; wherein at least one of the current supplying portions is connected to one of the bit lines according to the number of the switching elements connected to the bit line.
With this configuration, when fabricating a read only memory, current supply to the bit line is effected with current supplying capabilities according to varying write data by merely controlling the connection or the disconnection between the current supplying portions and the bit line, and the portions except the connection or the disconnection can be communized between the read only memories having different write data. Therefore, automatic design layout of the elements or the like for the read only memory is easily achieved, and the fabrication can be facilitated as a result of the simplification of the fabrication process. Moreover, in the process of forming contacts after the formation of transistors, current supplying capabilities can be set in addition to ROM data, and this contributes to a reduction in the lead time from the time when the ROM data are decided until the entire fabrication process is completed.
In accordance with yet another aspect of the invention, a read only memory is provided comprising: a plurality of switching elements provided so as to be connectable to and/or disconnectable from bit lines; wherein data to be read out are set by connecting and/or disconnecting the switching elements to/from the switching elements from the bit lines; and wherein, when reading out data, data corresponding to the presence or absence of switching elements connected to the bit lines are read out by discharging electric charge precharged in the bit lines with the switching elements selected by word lines; wherein the read only memory has a plurality of current supplying portions that constitute a current supplying circuit and are provided so as to be connectable to and/or disconnectable from the bit lines, the current supplying portions supplying electric current to the bit lines when the switching elements are selected by the word lines.
With this configuration, it is made possible to set the number of current supplying portions that are connected to a bit line in a data writing in read only memories in which data can be set (written) after the manufacture as well. Therefore, by appropriately compensating the off leakage current as described above, malfunctions and operation speed reductions are prevented.